1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory system, and more particularly, it relates to a semiconductor memory device and a memory system using an electrically rewritable and non-volatile semiconductor memory in combination with an electrically rewritable and volatile semiconductor memory.
2. Description of the Related Art
Conventionally, there is known an EEPROM (Electrically Erasable and Programmable Read Only Memory) as one of the semiconductor memories. Special attention has been paid to a NAND-type flash memory using a plurality of memory cells connected in series to constitute a NAND cell block, as memory capable of high integration.
For the NAND-type flash memory, see the following references: F. Masuoka et al., “New ultra high density EPROM and flash EEPROM with NAND structured cell”, IEDM Tech. Dig., pp. 552–555, December 1987; J. K. Kim et al., “A 120 mm2 64 Nb NAND flash memory achieving 180 ns/Byte effective program speed”, IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 670–680, May 1997.
A memory cell transistor constituting the NAND-type flash memory has an MOS transistor structure in which a floating gate (charge accumulation layer) and a control gate are stacked one on the other via an insulation film on a semiconductor substrate. A plurality of the memory cell transistors are arranged adjacent to each other and connected in series so as to share a source and a drain, thereby constituting a NAND-type cell. Such NAND cells are arranged in matrix like layout to thereby constitute a memory cell array of the NAND-type flash memory.
The NAND-type cells arranged in the column direction of the memory cell array have one end composed of memory cell transistors having drains each connected via a select gate transistor to a common bit line, and the other end composed of memory cell transistors having sources each connected via a select gate transistor to a common source line. Control gates of the memory cell transistors and select gates of the select gate transistors are connected in the row direction of the cell array as a word line (control gate line) and a select gate line, respectively.
The NAND-type flash memory having the aforementioned configuration has advantages that the cell size per one bit is small and the rewrite speed is high as compared to a NOR-type flash memory. On the other hand, the NAND-type flash memory has a disadvantage that access time in random access is 25 μs which is 2 orders or more slower than the NOR-type flash memory whose access time is 100 ns.
For the NOR-type flash memory, see the following references: F. Masuoka et al., “A new flash E2PROM cell using triple polysilicon technology”, IEDM Tech. Dig., pp. 464–467, December 1984; G. Samachisa et al., “A 128K flash EEPROM using double polysilicon technology”, ISSCC Dig. Tech. Papers, pp. 76–77, February 1987; V. N. Kynett et al., “An in-system reprogrammable 256K CMOS flash memory”, ISSCC Dig. Tech. Papers, pp. 132–133, February 1988.
Moreover, in the NAND-type flash memory, 512-byte data items are read out all at once as page data into a page buffer and accordingly, it is recommended to perform error check correction (hereinafter, referred to as ECC) from an external system out of the chip. Moreover, there is a disadvantage that 16-byte redundant bits per page should be provided on the chip.
Accordingly, to constitute a semiconductor memory device and memory system using the NAND-type flash memory in combination with an SRAM (Static Random Access Memory), a part of a peripheral circuit of the NAND-type flash memory including an ECC circuit and a control circuit of the NAND flash memory and an interface circuit interfacing with the high speed SRAM should be provided as a separate chip.
Especially with the mobile telephone and PDA (Personal Digital Assistant) market becoming larger and larger every year in all the world, the flash memory used for mobile telephones and PDAs should significantly increase its capacity. Demand for the NAND-type flash memory is increasing because its bit cost is cheap compared to that of the NOR-type flash memory.
However, as has been described above, when a part of the peripheral circuit of the NAND-type flash memory including the ECC circuit and the control circuit dedicated to the NAND-type flash memory and interface circuit for the high-speed SRAM is provided on a separate chip, this not only increases a production cost but also causes a large obstacle when trying to reduce the size of the mobile telephone and the like.
Ideally speaking, it is preferable that all the peripheral circuits of a memory chip be implemented on a single memory chip. However, the NAND-type flash memory requires voltage as high as about 20V for memory data rewriting, and for designing a high-voltage transistor, a large design rule is applied to the peripheral circuit.
For this, in the semiconductor memory device and memory system using the NAND-type flash memory in combination with the high-speed SRAM, an overhead area as a redundant area arises in layout when all the peripheral circuits of the NAND-type flash memory are formed on the chip of the NAND-type flash memory.
Moreover, as has been described above, the memory cell transistor of the NAND-type flash memory has a two-layered gate structure in which a floating gate and a control gate are stacked one on the other. Here, if a MOS transistor having an ordinary one-layered gate structure is used to constitute a peripheral circuit of the cell array, separate steps are required for forming the cell array and the peripheral circuit, which increases the production cost.
For this, conventionally, in the NAND-type flash memory production procedure, all the MOS transistors including the peripheral circuit are formed to have the two-layered gate structure and in the MOS transistors constituting the peripheral circuit, the floating gate and the control gate are connected to each other and pulled out onto a wiring layer, so as to obtain substantially a one-gate structure.
However, a large area is required for a contact portion for connecting the floating gate and the control gate and pulling them out onto the wiring layer. Accordingly, if this method is used for all the MOS transistors required for the peripheral circuit structure, it becomes difficult to reduce the occupation area of the peripheral circuit.
Especially, in the semiconductor memory device and memory system using the NAND-type flash memory in combination with the high-speed SRAM, if all the peripheral circuits related to the NAND-type flash memory including not only a peripheral circuit for operation of the NAND-type flash memory but also the ECC circuit, the control circuit of the NAND-type flash memory, and the interface circuit for interfacing between the NAND-type flash memory and the high-speed SRAM are formed on the chip of the NAND-type flash memory, the chip size becomes excessively large.
For this, in spite of causing a large size and a high cost of the mobile telephone and the like, in the semiconductor memory device and memory system using the NAND-type flash memory in combination with the high-speed SRAM, a widely used design method is such that a part of the peripheral circuit dedicated to the NAND-type flash memory is implemented on a separate chip.
It is therefore an aspect of the present invention to provide a semiconductor memory device and memory system using a non-volatile semiconductor memory consisting of a NAND-type flash memory and the like in combination with a volatile semiconductor memory consisting of a high-speed SRAM in which a part of the peripheral circuit dedicated to the NAND-type flash memory is not formed on a separate chip but provided on the high-speed SRAM, thereby reducing the size of the mobile telephone and the like.